1. Field of the Invention
A present invention relates to a semiconductor memory device, and more particularly to the partial structure of a word line drive circuit.
2. Related Art
Scaling for power supply voltage is effective for reduction of power consumption of a CMOS semiconductor integrated circuit. However, in the case of an SRAM widely used in a system LSI, scaling for power supply voltage tends to occur degradation of characteristics caused by the construction of a memory cell circuit. The main reason is that variation of threshold voltage occurred the back bias effect remarkably reduces current performance when a power supply voltage is low. The back bias effect is caused by potential isolation of a source drain of an access transistor from a substrate potential.
Thus, the performance of releasing the charge on bit lines is reduced in the SRAM in reading. Accordingly, the bit line delay increases. Additionally, in writing, time for rewriting hold data increases. Moreover, when the voltage is extremely low, it is impossible to rewrite in a DC manner.
In order to reduce such characteristic degradation, the power supply voltage supplied to a word line is higher than the other circuit portions in a related art.
FIG. 9 is a circuit diagram showing a construction of a semiconductor memory device in a related art. FIG. 9 shows one word line, a word line drive circuit for driving it, and memory cells connected to the word line (For example, Japanese Laid-Open Publication Kokai No. HEI 2-118992 (page 2–3, FIG. 1)).
In FIG. 9, reference numerals 11 and 12 represent a p-channel drive transistor and an n-channel drive transistor for driving a word line WL, respectively. Reference numeral 44 represents a level shift circuit. A word line drive circuit 400 is composed of them. Reference numeral 17 represents a memory cell.
A gate of an access transistor of a plurality of memory cells 17 is connected to the word line WL. An input NWL of the word line drive circuit 400 is provided to each gate of the p-channel drive transistor 11 and the n-channel drive transistor 12 through the level shift circuit 44.
A power supply voltage VDDH supplied to the p-channel drive transistor 11 and the n-channel drive transistor 12 is higher than a power supply voltage VDDL of the memory cell 17, and a high-level potential VDDL of the input NWL of the word drive circuit 400.
As shown in FIG. 10, when the input NWL of the word line drive circuit 400 changes to a low level, the p-channel drive transistor 11 turns ON, and then the voltage VDDH higher than the power supply voltage VDDL of the memory cell 17 is supplied to the word line WL. Thus, performance deterioration caused by the back bias effect of the access transistor in the memory cell 17 is reduced, and operating characteristics are improved.
When the input NWL of the word line drive circuit 400 is a high level, the level shift circuit 44 pulls up the gate input of the p-channel drive transistor 11 to the VDDH level. The level shift circuit 44 plays a role to reduce the subthreshold leakage current in an OFF state of the p-channel drive transistor 11.
Thus, almost all the portions of the SRAM circuit are operated at a low power supply voltage, and only the word line drive circuit 400, which is even a small portion, is operated at a high voltage. Accordingly, power consumption can be effectively reduced without characteristic degradation.
However, in the above related art, one more power supply voltage is required. Accordingly, the layout design of an LSI chip should be complicated. Additionally, two areas for power supply wiring are required. Therefore, the chip area increases. Moreover, two power supply circuits are required for the design of a system side using such a semiconductor device. This increases substrate mount area. Such a semiconductor device has a disadvantage in cost.
When the system side has one power supply and one more power supply circuit is separately provided on the chip, its chip area further increases.